1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to a technique for self-aligning the gate region between the drain and source of a field effect transistor.
2. Description of the Prior Art
In the fabrication of metal nitride oxide semiconductor (MNOS) transistors a variable threshold gate region is located between two fixed threshold gate regions. The three gate regions are between the drain and source of the transistor. The density of an array of MNOS transistors is limited by the drain to source spacing of each transistor which as previously mentioned contains a fixed threshold region, a variable threshold region and a second fixed threshold region. Using present processing techniques, a 1.5 micrometer side diffusion occurs during diffusion of a 4 micrometer wide P+ stripe for each of the drain and source regions of one or more transistors which are formed in parallel therebetween. A 1 micrometer alignment tolerance occurs between the several masks used in the process steps. The 1 micrometer alignment tolerance and the side diffusion of 1.5 micrometers reduce the space between the drain and source for the first fixed threshold region, the variable threshold region and the second fixed threshold region from 14 micrometers to 9 micrometers. With a variable threshold region space of 5 micrometers the space between the variable threshold region to either the drain or source could be reduced from 4.5 micrometers to 2 micrometers. This is the channel length for the fixed threshold regions or non-memory regions. Present photo engraving techniques allow for a drain and source minimum width of 4 micrometers comprised of P+ material in an N-type substrate and a variable threshold region of 5 micrometers in width.
A transistor having a fixed threshold region followed by a variable threshold region followed by a fixed threshold region was described and shown in FIG. 3 in U.S. Pat. No. 3,719,866 which issued on Mar. 6, 1973 to C. T. Naber and G. C. Lockwood and assigned to the National Cash Register Company of Dayton, Ohio.
In U.S. Pat. No. 4,053,917 which issued on Oct. 11, 1977 to F. C. Blaha, J. R. Cricchi and M. H. White and assigned to the United States of America, a drain source protected MNOS transistor is described wherein the fixed threshold regions have their gate oxide grown subsequent to the formation of the gate oxide and nitride region of the variable threshold transistor. The gate oxide of the fixed threshold regions are grown concurrently on either side of the variable threshold region to the drain and source respectively. In U.S. Pat. No. 4,053,917 the gate region of the fixed and variable threshold regions are not self-aligned with the drain and source regions.
It is therefore desirable to provide a drain source protected MNOS memory having the drain and source regions and the variable threshold region aligned with respect to each other.
It is further desirable to provide a process for making high density variable threshold transistors.
It is further desirable to use ion implantation to form the source and drain regions and at the same time to self-align the variable threshold portion of the memory transistor.
It is further desirable to provide diffused drain and source regions while at the same time having a self-aligned variable threshold transistor region between the drain and source regions of the memory transistor.